library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cache is port(cacheIn: in std_logic_vector(155 downto 0); cacheOut: out std_logic_vector(155 downto 0); cachePos: in std_logic_vector(5 downto 0); -- posição da cache WR: in std_logic; RD: in std_logic; CLK: in std_logic); -- SE 0 = primeiro conjunto, SE 1 = segundo conjunto end entity; architecture comportamental of cache is type mem is array(63 downto 0) of std_logic_vector(155 downto 0) ; signal sigMem: mem :=(others => (others=>'0')); --inicializa com zero begin process(CLK,WR,sigMem,cachePos,cacheIn) begin if(CLK'event and CLK='1' and WR='1' ) then for i in 0 to 155 loop if (cacheIn(i)='0' or cacheIn(i)='1') then sigMem(conv_integer(cachePos))(i) <= cacheIn(i); else sigMem(conv_integer(cachePos))(i) <= sigMem(conv_integer(cachePos))(i); end if; end loop; end if; if(CLK'event and CLK='1' and RD='1') then cacheOut <= sigMem(conv_integer(cachePos)); end if; end process; end comportamental;