game Project Status (05/04/2014 - 11:03:14)
Project File: Gamedisplay.xise Parser Errors: No Errors
Module Name: game Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 47 9,312 1%  
Number of 4 input LUTs 241 9,312 2%  
Number of occupied Slices 136 4,656 2%  
    Number of Slices containing only related logic 136 136 100%  
    Number of Slices containing unrelated logic 0 136 0%  
Total Number of 4 input LUTs 269 9,312 2%  
    Number used as logic 241      
    Number used as a route-thru 28      
Number of bonded IOBs 13 232 5%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentsų 4. maj 11:02:41 2014000
Translation ReportCurrentsų 4. maj 11:02:45 2014000
Map ReportCurrentsų 4. maj 11:02:48 2014002 Infos (0 new)
Place and Route ReportCurrentsų 4. maj 11:03:01 2014002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentsų 4. maj 11:03:03 2014006 Infos (0 new)
Bitgen ReportCurrentsų 4. maj 11:03:08 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datesų 4. maj 10:09:00 2014
WebTalk ReportCurrentsų 4. maj 11:03:08 2014
WebTalk Log FileCurrentsų 4. maj 11:03:14 2014

Date Generated: 05/04/2014 - 11:03:14