library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.signed;

entity parity_int is 
  port( clk : in std_logic;
        reset: in std_logic;
        nm_sh_sel:in std_logic;
        code_rate:in std_logic_vector(3 downto 0);
        K_ldpc: in std_logic_vector(15 downto 0);
        N_ldpc:in std_logic_vector(15 downto 0);
        input1: in std_logic;
        output1: out std_logic);
         
  end parity_int;
   
  architecture arch of parity_int is  
  --Both normal and short are in one array. if we select normal then it gives 0 to 9 and 
  -- if we select the short then code_rate plus 6 need to add.
  type Q_ldpc_normal is array (0 to 14) of integer;
  constant Q_ldpc:Q_ldpc_normal:=(90,72,60,45,36,30,36,30,27,25,18,15,12,10,8);
  
  signal count1:integer;
  signal s:integer;
  signal t:integer;
  signal temp0:std_logic_vector(0 to 64799);
  signal cd_rate:std_logic_vector(3 downto 0);
  
  begin
  cd_rate <= code_rate when nm_sh_sel = '0' else code_rate + 6 ;  
    
    process(clk,reset)
       begin
         if((clk'event and clk = '1') or reset = '1') then
           if reset = '1' then
             count1 <= 0;
           else
             if count1 = to_integer(unsigned(N_ldpc)) + to_integer(unsigned(K_ldpc)) + 1 then --32400+64800
               count1 <= 0;
             else
             count1 <= count1 + 1;
           end if;
         end if;
       end if;
     end process;
     
      process(count1,t)
       begin
         
           if reset = '1' then
             s <= 0;
           else
             
             if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) +1 then 
            
             if s = 360 then
                s <= 0;
               
             else
                
                s <= s + 1;
           
           end if;
         end if;
       end if;
     end process;
     
      process(count1)
       begin
        
           if reset = '1' then
             t <= 0;
           else
             if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 then              
             if t = Q_ldpc(to_integer(unsigned(cd_rate)))   then
                t <= 0;
               
             else
               
               if s = 360 then
                t <= t + 1;
              end if;
           end if;
         end if;
       end if;
     end process;
     
     process(count1,reset)
       begin
         if count1 >= 1 and  count1 < to_integer(unsigned(K_ldpc)) + 1  then
         temp0(count1 - 1) <= input1; -- it took one extra cycle because input delay by one cycle... 
         
       elsif count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 and t < 90 then
         temp0(to_integer(unsigned(K_ldpc)) + (360 * t) + s ) <= input1;
         output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1);----32401-32400-1=0
         
       elsif count1 >= to_integer(unsigned(N_ldpc)) + 1 and count1 < (to_integer(unsigned(N_ldpc)) + to_integer(unsigned(K_ldpc)) + 1) then
         output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1);
         
       end if;
  
end process;
end arch;