library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rom is port(addr:in std_logic_vector(3 downto 0); clock:in std_logic; rom_enable:in std_logic; dout:out std_logic_vector(7 downto 0)); end rom; architecture beh123 of rom is type rom_arr is array(0 to 15)of std_logic_vector(7 downto 0); constant mem:rom_arr:= ("01100000","01010000","01100000","00000000","11110011","10110000","11010000","00100000","11110000","UUUUUUUU","UUUUUUUU","01000000","UUUUUUUU","UUUUUUUU","UUUUUUUU","UUUUUUUU"); begin process(clock) begin if rom_enable='1' then if (clock'event and clock='1') then dout<=mem(conv_integer(addr)); end if; end if; end process; end beh123;