library ieee; use ieee.std_logic_1164.all; entity MUX is port(d0,d1:in std_logic_vector(7 downto 0); s:in std_logic; y:out std_logic_vector(7 downto 0) ); end MUX; architecture MUX_arch of MUX is begin process(d0,d1,s) begin case s is when '0'=> y<=d0; when '1'=> y<=d1; when others=> y<="ZZZZZZZZ"; end case; end process; end MUX_arch;