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------|																				|------
------|		Controle d'un feu de circulation en utilisant les Machines d'Etats		|------
------|				Control of the traffic light using machines States				|------
------|																				|------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

---------------------------------------
---		Entity						---
---------------------------------------
entity feu_circulation is
	port(	clk,rst,tst,a: in bit;
			r1,r2:out std_logic_vector(2 downto 0));
end feu_circulation;

---------------------------------------
---		Architecture				---
---------------------------------------
architecture feu_circulation of feu_circulation is
	type etat is(R_V,R_O,V_R,O_R,O_O);
	signal p_etat,s_etat:etat;
	signal clk_etat,clk_s:bit:='0';
	signal cnt,tmps:integer:=1;
begin

------------------------------------------------------------------------------
---		Changement de l'Etat Presente vers l'Etat Suivante			       ---
------------------------------------------------------------------------------
	process(rst,clk_etat)
	begin
		if rst='1' then
			p_etat<=R_V;
		elsif(clk_etat'event and clk_etat='1') then
			p_etat<=s_etat;
		end if;
	end process;
------------------------------------------------------------------------------------
---		Definition de l'Etat Suivante et les valeurs des Signaux de Sortie		---
---						Changing Presente State to Next State					---
------------------------------------------------------------------------------------
	process(p_etat,a,tst)
	begin
		case p_etat is
			when R_V =>r1<="100";	r2<="010";
				if a='0' then
					s_etat<=R_O;
				else
					s_etat<=O_O;
				end if;
				if tst='0' then	tmps<=30;	else	tmps<=1;	end if;
			when R_O =>r1<="100";	r2<="001";
				if a='0' then
					s_etat<=V_R;
				else
					s_etat<=O_O;
				end if;
				if tst='0' then	tmps<=5;	else	tmps<=1;	end if;
			when V_R =>r1<="010";	r2<="100";
				if a='0' then
					s_etat<=O_R;
				else
					s_etat<=O_O;
				end if;
				if tst='0' then	tmps<=45;	else	tmps<=1;	end if;
			when O_R =>r1<="001";	r2<="100";
				if a='0' then
					s_etat<=R_V;
				else
					s_etat<=O_O;
				end if;
				if tst='0' then	tmps<=5;	else	tmps<=1;	end if;
			when O_O =>r1<="001";	r2<="001";
				if a='0' then
					s_etat<=R_V;
				else
					s_etat<=O_O;
				end if;
				tmps<=1;
		end case;
	end process;
---------------------------------------------------------------------------------------------------------
---	Génération de l'horloge de 1s de période (clk_s) à partir de l'horloge de 8ns de période (clk)	---
---				Generation of the clock period of 1s (clk_s) from the clock period of 8ns (clk)		---
---------------------------------------------------------------------------------------------------------
	process(clk,rst)
	begin
		if rst='1' then
			cnt<=1;
		else
			cnt<=cnt+1;
		end if;
		if cnt<125 then--- to use clock periode of 8ns, use cnt<125000000. note: It doesn't work in ISE Simulation
			clk_s<='0';	 -- to use clock periode of 8us, use cnt<125000.		
		else				 -- to use clock periode of 8ms, use cnt<125.
			clk_s<='1';
		end if;
		if cnt=250 then--- to use clock periode of 8ns, use cnt<250000000. note: It doesn't work in ISE Simulation
			cnt<=1;		 -- to use clock periode of 8us, use cnt<250000.		
		end if;			 -- to use clock periode of 8ms, use cnt<250.
	end process;
--------------------------------------------------------------------------------------------------
---	Géneration de l'horloge de sorite (clk_etat) d'une période qui varie selon les 3 Modes   ---
---		Generation of the output clock (clk_etat) of a period which varies from 3 Modes		  ---
--------------------------------------------------------------------------------------------------
	process(clk_s,rst,a,tst)
		variable temps:integer;
		variable ok:bit:='1';
	begin
		if tst='1' then
			ok:='1';
		end if;
		if rst='1' then 
				ok:='1';
		elsif a='0' then
				if ok='1' then
					temps:=tmps;
					ok:='0';
					clk_etat<='0';
				end if;
				if clk_s'event and clk_s='1' then
					temps:=temps-1;
					if temps=0 then
						ok:='1';
						clk_etat<='1';
					end if;
				end if;
		end if;
		if a='1' then
			clk_etat<=clk_s;
			ok:='1';
		end if;
	end process;
end feu_circulation;
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-----	Abdallah -----------	Abdallah -------------	Abdallah ----------	Abdallah --------
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