library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;  
use ieee.std_logic_arith.all;

ENTITY trainticket_machine_tb IS
END trainticket_machine_tb;
 
ARCHITECTURE behavior OF trainticket_machine_tb IS 
 
   Signal Clock,Reset,Cancel,RM1,RM2,RM5,KL_station,Mid_station,Klang_station : std_logic := '0';
	Signal Ticket : std_logic ;
	signal Change,Retrn,Money_sum : std_logic_vector(3 downto 0);
   constant Clock_period : time := 10 ns;
 
BEGIN
 
   uut: entity work.trainticket_machine PORT MAP (
          Clock => Clock,
          Reset => Reset,
          Cancel => Cancel,
          RM1 => RM1,
          RM2 => RM2,
          RM5 => RM5,
          KL_station => KL_station,
          Mid_station => Mid_station,
          Klang_station => Klang_station,
			 Ticket => Ticket,
          Change => Change,
          Retrn => Retrn
        );
		  
	Clock_process :process
   begin
        Clock <= '0';
        wait for Clock_period/2;
        Clock <= '1';
        wait for Clock_period/2;
   end process;
	
   -- Stimulus process
   stim_proc: process
   begin		
		
		wait for Clock_period*2;
		Reset <= '1';
		wait for Clock_period;
		Reset <= '0';
		wait for Clock_period;
		Cancel <= '1';
		wait for Clock_period;
		Cancel <= '0';
		wait for Clock_period;
		KL_station <= '1';
		wait for Clock_period;
		KL_station <= '0';
		wait for Clock_period;
		Mid_station <= '1';
		wait for Clock_period;
		Mid_station <= '0';
		wait for Clock_period;
		Klang_station <= '1';
		wait for Clock_period;
		Klang_station <= '0';
		wait for Clock_period;
		RM1 <= '1';
		wait for Clock_period;
		RM1 <= '0';
		wait for Clock_period;
		RM2 <= '1';
		wait for Clock_period;
		RM2 <= '0';
		wait for Clock_period;
		RM5 <= '1';
		wait for Clock_period;
		RM5 <= '0';
		wait for Clock_period;
      wait;
   end process;

END;