LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; use ieee.MATH_REAL.all; ENTITY tb_fmdemod IS END tb_fmdemod; ARCHITECTURE behavior OF tb_fmdemod IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fmdemod PORT( clk : IN std_logic; din : IN std_logic_vector(7 downto 0); dout : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal din : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal dout : std_logic_vector(7 downto 0); -- Clock period definitions signal nscnt1 : integer := 0; signal nscnt2 : integer := 0; signal modval : integer := 0; signal ramp : integer := 10000; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fmdemod PORT MAP ( clk => clk, din => din, dout => dout ); clk <= not clk after 5 ns; process -- generate fm sinus signal begin wait for 1 ns; -- generate linear ramp --> saw tooth modulation if ramp<300000 then ramp <= ramp+1; else ramp <= 0; end if; modval <= 10000 + ramp/30; -- generate slow sine for modulation if nscnt2<500000 then nscnt2 <= nscnt2+1; else nscnt2 <= 0; end if; -- modval <= 10000 + integer( (1.0 + cos(2.0*MATH_PI*real(nscnt2)/real(500000))) *5000.0); -- generate if nscnt1