library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; -------------------------- -------------------------- package type_def_pack is constant s: integer := 5; constant line_width: integer := 1; type wire is array (2**s -1 downto 0) of std_logic_vector(line_width-1 downto 0); end package; -------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library work; use work.type_def_pack.all; -------------------------- entity Generic_Mux is port ( Dinput : in wire; sel : in std_logic_vector (s-1 downto 0); output : out std_logic_vector(line_width-1 downto 0)); end Generic_Mux; ------------------------- architecture behavioral of Generic_Mux is BEGIN output <= Dinput(conv_integer(sel))(line_width-1 downto 0); END architecture behavioral; ------------------------- ------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.type_def_pack.all; ------------------------- ------------------------- entity TB_GenMux is end TB_GenMux; ------------------------- architecture behavioral of TB_GenMux is type ARY is array (2**s -1 downto 0) of std_logic_vector(line_width-1 downto 0); signal TDinput : wire; signal Tsel: std_logic_vector (s-1 downto 0); signal Toutput: std_logic_vector(line_width-1 downto 0); signal temp1: ARY; signal temp2: wire; component Generic_Mux is port ( Dinput : in wire; sel : in std_logic_vector (s-1 downto 0); output : out std_logic_vector(line_width-1 downto 0)); end component; begin UUT: Generic_Mux port map ( Dinput => TDinput, sel => Tsel, output => Toutput); temp1(0)<= std_logic_vector(to_signed (1,line_width)); temp1(1)<= std_logic_vector(to_signed (0,line_width)); temp1(2)<= std_logic_vector(to_signed (1,line_width)); temp1(3)<= std_logic_vector(to_signed (1,line_width)); temp1(4)<= std_logic_vector(to_signed (0,line_width)); temp1(5)<= std_logic_vector(to_signed (0,line_width)); temp1(6)<= std_logic_vector(to_signed (1,line_width)); temp1(7)<= std_logic_vector(to_signed (0,line_width)); temp1(8)<= std_logic_vector(to_signed (0,line_width)); temp1(9)<= std_logic_vector(to_signed (0,line_width)); temp1(10)<= std_logic_vector(to_signed (0,line_width)); temp1(11)<= std_logic_vector(to_signed (0,line_width)); temp1(12)<= std_logic_vector(to_signed (1,line_width)); temp1(13)<= std_logic_vector(to_signed (1,line_width)); temp1(14)<= std_logic_vector(to_signed (1,line_width)); temp1(15)<= std_logic_vector(to_signed (0,line_width)); temp1(16)<= std_logic_vector(to_signed (1,line_width)); temp1(17)<= std_logic_vector(to_signed (1,line_width)); temp1(18)<= std_logic_vector(to_signed (0,line_width)); temp1(19)<= std_logic_vector(to_signed (0,line_width)); temp1(20)<= std_logic_vector(to_signed (1,line_width)); temp1(21)<= std_logic_vector(to_signed (0,line_width)); temp1(22)<= std_logic_vector(to_signed (0,line_width)); temp1(23)<= std_logic_vector(to_signed (1,line_width)); temp1(24)<= std_logic_vector(to_signed (1,line_width)); temp1(25)<= std_logic_vector(to_signed (1,line_width)); temp1(26)<= std_logic_vector(to_signed (1,line_width)); temp1(27)<= std_logic_vector(to_signed (0,line_width)); temp1(28)<= std_logic_vector(to_signed (1,line_width)); temp1(29)<= std_logic_vector(to_signed (1,line_width)); temp1(30)<= std_logic_vector(to_signed (0,line_width)); temp1(31)<= std_logic_vector(to_signed (1,line_width)); temp2(0)(line_width-1 downto 0) <= temp1(0); temp2(1)(line_width-1 downto 0) <= temp1(1); temp2(2)(line_width-1 downto 0) <= temp1(2); temp2(3)(line_width-1 downto 0) <= temp1(3); temp2(4)(line_width-1 downto 0) <= temp1(4); temp2(5)(line_width-1 downto 0) <= temp1(5); temp2(6)(line_width-1 downto 0) <= temp1(6); temp2(7)(line_width-1 downto 0) <= temp1(7); temp2(8)(line_width-1 downto 0) <= temp1(8); temp2(9)(line_width-1 downto 0) <= temp1(9); temp2(10)(line_width-1 downto 0) <= temp1(10); temp2(11)(line_width-1 downto 0) <= temp1(11); temp2(12)(line_width-1 downto 0) <= temp1(12); temp2(13)(line_width-1 downto 0) <= temp1(13); temp2(14)(line_width-1 downto 0) <= temp1(14); temp2(15)(line_width-1 downto 0) <= temp1(15); temp2(16)(line_width-1 downto 0) <= temp1(16); temp2(17)(line_width-1 downto 0) <= temp1(17); temp2(18)(line_width-1 downto 0) <= temp1(18); temp2(19)(line_width-1 downto 0) <= temp1(19); temp2(20)(line_width-1 downto 0) <= temp1(20); temp2(21)(line_width-1 downto 0) <= temp1(21); temp2(22)(line_width-1 downto 0) <= temp1(22); temp2(23)(line_width-1 downto 0) <= temp1(23); temp2(24)(line_width-1 downto 0) <= temp1(24); temp2(25)(line_width-1 downto 0) <= temp1(25); temp2(26)(line_width-1 downto 0) <= temp1(26); temp2(27)(line_width-1 downto 0) <= temp1(27); temp2(28)(line_width-1 downto 0) <= temp1(28); temp2(29)(line_width-1 downto 0) <= temp1(29); temp2(30)(line_width-1 downto 0) <= temp1(30); temp2(31)(line_width-1 downto 0) <= temp1(31); TDinput <= temp2; P1:process begin Tsel <= "00000"; wait for 10 ns; Tsel <= "00001"; wait for 10 ns; Tsel <= "00010"; wait for 10 ns; Tsel <= "00011"; wait for 10 ns; Tsel <= "00100"; wait for 10 ns; Tsel <= "00101"; wait for 10 ns; Tsel <= "00110"; wait for 10 ns; Tsel <= "00111"; wait for 10 ns; Tsel <= "01000"; wait for 10 ns; Tsel <= "01001"; wait for 10 ns; Tsel <= "01010"; wait for 10 ns; Tsel <= "01011"; wait for 10 ns; Tsel <= "01100"; wait for 10 ns; Tsel <= "01101"; wait for 10 ns; Tsel <= "01110"; wait for 10 ns; Tsel <= "01111"; wait for 10 ns; Tsel <= "10000"; wait for 10 ns; Tsel <= "10001"; wait for 10 ns; Tsel <= "10010"; wait for 10 ns; Tsel <= "10011"; wait for 10 ns; Tsel <= "10100"; wait for 10 ns; Tsel <= "10101"; wait for 10 ns; Tsel <= "10110"; wait for 10 ns; Tsel <= "10111"; wait for 10 ns; Tsel <= "11000"; wait for 10 ns; Tsel <= "11001"; wait for 10 ns; Tsel <= "11010"; wait for 10 ns; Tsel <= "11011"; wait for 10 ns; Tsel <= "11100"; wait for 10 ns; Tsel <= "11101"; wait for 10 ns; Tsel <= "11110"; wait for 10 ns; Tsel <= "11111"; wait for 10 ns; end process; end architecture behavioral;