library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; -------------------------- -------------------------- entity mux_tb is generic ( s : integer := 3; line_width : NATURAL := 8); end mux_tb; ------------------------- ------------------------- architecture behavioral of mux_tb is signal TDinput : std_logic_vector ((2**s)*line_width -1 downto 0); signal Tsel : std_logic_vector (s-1 downto 0); signal Toutput : std_logic_vector (line_width-1 downto 0); component Generic_Mux is generic ( s : integer := 3; line_width : integer := 8); port ( Dinput : in std_logic_vector ((2**s)*line_width -1 downto 0); sel : in std_logic_vector (s-1 downto 0); output : out std_logic_vector (line_width-1 downto 0)); end component; begin UUT : Generic_Mux generic map ( s => s , line_width => line_width) port map ( Dinput => TDinput, sel => Tsel , output => Toutput); P:process begin --conv_std_logic_vector (43,line_width) -- std_logic_vector (to_signed(43,line_width)); --std_logic_vector ("00101011") TDinput (line_width-1 downto 0)<= std_logic_vector (to_signed(43,line_width)); TDinput (line_width*2-1 downto line_width)<= std_logic_vector (to_signed (109,line_width)); TDinput (line_width*3-1 downto line_width*2)<= std_logic_vector (to_signed (124,line_width)); TDinput (line_width*4-1 downto line_width*3)<= std_logic_vector (to_signed (116,line_width)); TDinput (line_width*5-1 downto line_width*4)<= std_logic_vector (to_signed (74,line_width)); TDinput (line_width*6-1 downto line_width*5)<= std_logic_vector (to_signed (15,line_width)); TDinput (line_width*7-1 downto line_width*6)<= std_logic_vector (to_signed (51,line_width)); Tsel <= "000"; wait for 10 ns; Tsel <= "001"; wait for 10 ns; Tsel <= "010"; wait for 10 ns; Tsel <= "011"; wait for 10 ns; Tsel <= "100"; wait for 10 ns; Tsel <= "101"; wait for 10 ns; Tsel <= "110"; wait for 10 ns; Tsel <= "111"; wait for 10 ns; end process; end architecture behavioral;