LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY TTT_tb IS END TTT_tb; ARCHITECTURE behavior OF TTT_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT TTT Generic ( N : integer := 3 ); Port ( Rst_n, clk : in std_logic; D_in : in std_logic_vector (1 downto 0); Stts : out std_logic_vector (1 downto 0)); END COMPONENT; --Inputs signal Rst_n : std_logic := '0'; signal clk : std_logic := '0'; signal D_in : std_logic_vector(1 downto 0) := (others => '0'); --Outputs signal Stts : std_logic_vector(1 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; constant N : integer := 3; BEGIN -- Instantiate the Unit Under Test (UUT) uut: TTT PORT MAP ( Rst_n => Rst_n, clk => clk, D_in => D_in, Stts => Stts ); clk <= not clk after 10 ns; process begin Rst_n <= '0'; D_in <= "00"; -- initialization wait until falling_edge(clk); wait until falling_edge(clk); Rst_n <= '1'; for i in 1 to n-1 loop -- case in which O (10) wins [row] for j in 1 to n loop D_in <= "00"; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); end loop; for j in 1 to n loop D_in <= "10"; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); Rst_n <= '0'; wait until falling_edge(clk); Rst_n <= '1'; for i in 1 to n-1 loop -- case in which X (01) wins [row] for j in 1 to n loop D_in <= "00"; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); end loop; for j in 1 to n loop D_in <= "01"; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); Rst_n <= '0'; wait until falling_edge(clk); Rst_n <= '1'; for i in 1 to n loop -- case in which O (10) wins [coulmn] for j in 1 to n loop if j = 1 then D_in <= "10"; else D_in <= "01"; end if; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); end loop; wait until falling_edge(clk); Rst_n <= '0'; wait until falling_edge(clk); Rst_n <= '1'; for i in 1 to n loop -- case in which X (01) wins [coulmn] for j in 1 to n loop if j = 1 then D_in <= "01"; else D_in <= "10"; end if; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); end loop; wait until falling_edge(clk); Rst_n <= '0'; wait until falling_edge(clk); Rst_n <= '1'; for i in 1 to n-1 loop -- case of draw for j in 1 to n loop D_in <= "00"; wait until falling_edge(clk); end loop; D_in <= "11"; wait until falling_edge(clk); end loop; for j in 1 to n-1 loop D_in <= "01"; wait until falling_edge(clk); end loop; D_in <= "10"; wait until falling_edge(clk); D_in <= "11"; wait until falling_edge(clk); Rst_n <= '0'; wait until falling_edge(clk); wait until falling_edge(clk); wait; end process; END;