---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:29:41 10/02/2012 -- Design Name: -- Module Name: MMFlipFlop - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MMFlipFlop is Port ( D : in STD_LOGIC; CK : in STD_LOGIC; Q : out STD_LOGIC); end MMFlipFlop; architecture Behavioral of MMFlipFlop is COMPONENT MMLatch Port ( D : in STD_LOGIC; W : in STD_LOGIC; Z : out STD_LOGIC); end COMPONENT; COMPONENT mmINVERT Port ( a : in STD_LOGIC; z : out STD_LOGIC); end COMPONENT; SIGNAL M1 : STD_LOGIC; SIGNAL M2 : STD_LOGIC; SIGNAL M3 : STD_LOGIC; begin gate1 : MMLatch PORT MAP (D=>D, W=>M2, Z=>M1); gate2 : MMLatch PORT MAP (D=>M1, W=>CK, Z=>M3); gate3 : mmINVERT PORT MAP (a=>CK, z=>M2); Q<=M3; end Behavioral;