---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:56:05 06/26/2012 -- Design Name: -- Module Name: Serial_Converter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; Entity Serial_Converter is Port ( Parallel_Data : In Std_Logic_Vector (31 DOWNTO 0); Clk, Load : In Std_Logic; Serial_Out: Out Std_Logic); End Serial_Converter; Architecture Serial_Converter Of Serial_Converter is Signal reg: Std_Logic_Vector (31 DOWNTO 0); Begin Process (Clk) Begin If (Clk'EVENT And Clk='1') Then If (Load='1') Then reg <= Parallel_Data; Else reg <= reg(30 DOWNTO 0) & '0'; End If; End If; End Process; Serial_Out <= reg(31); End Serial_Converter;