-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:02:48 06/26/2012 -- Design Name: -- Module Name: C:/Documents and Settings/my computer/Desktop/an/Serial_converter/Serial_Convertertb.vhd -- Project Name: Serial_converter -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Serial_Converter -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.All; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Serial_Convertertb IS END Serial_Convertertb; ARCHITECTURE behavioral OF Serial_Convertertb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Serial_Converter PORT( Parallel_Data : IN std_logic_vector(31 downto 0); Clk : IN std_logic; Load : IN std_logic; Serial_Out : OUT std_logic ); END COMPONENT; --Inputs signal Parallel_Data : std_logic_vector(31 downto 0) := (others => '1'); signal Clk : std_logic := '0'; signal Load : std_logic := '0'; --Outputs signal Serial_Out : std_logic; -- Clock period definitions constant Clk_period : time := 10 ns; signal CNT : std_logic_vector(4 downto 0) := (others => '0'); BEGIN -- Instantiate the Unit Under Test (UUT) uut: Serial_Converter PORT MAP ( Parallel_Data => Parallel_Data, Clk => Clk, Load => Load, Serial_Out => Serial_Out ); -- Clock process definitions Clk_process :process begin Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process; -- Stimulus process stim_proc: process(Clk) begin CNT <= CNT + "00001"; end process; process (Clk) begin if (CNT = "00010") then Load <= '1'; else Load <= '0'; end if; end process; process (Clk) begin if (CNT = "00000") then Parallel_Data <= Parallel_Data ; end if; end process; END behavioral;