---------------------------------------------------------------------- -- Test Bench for fetch unit ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- Include globals use work.global.all; entity fetch_TB is -- entity declaration end fetch_TB; architecture TB of fetch_TB is component fetch is port( clock: in std_logic; clear: in std_logic; datOut:out std_logic_vector(N-1 downto 0) ); end component; -- Signals for wiring signal clock, clear : std_logic:='0'; signal Dataout : std_logic_vector(N-1 downto 0); begin DUT: fetch port map (clock, clear, Dataout); process begin clock <= '0'; wait for 10 ns; clock <= '1'; wait for 10 ns; end process; process -- Start of test bench run: begin clear <= '0'; wait for 300 ns; end TB;