`timescale 1ns/1ns

module DDR3 (
  clk,
  RESET,
  clkE);

input  clk;
input  RESET;
input  clkE;

wire clk_i;
wire RESET_i;
wire clkE_i;
integer i;


assign clk_i = clk;
assign RESET_i = RESET;
assign clkE_i = clkE;

DDR3_1 UDDR3_1 (
.clk_i  (clk_i),
.RESET_i  (RESET_i),
.clkE_i  (clkE_i));

endmodule

module DDR3_1 (
  clk_i,
  RESET_i,
  clkE_i);

input  clk_i;
input  RESET_i;
input  clkE_i;


reg  [255:0] s_clk;
reg  clk;
reg  clk_x;
reg  [255:0] s_RESET;
reg  RESET;
reg  RESET_x;
reg  [255:0] s_clkE;
reg  clkE;
reg  clkE_x;

integer i;

initial
begin
  s_RESET = "RESET";
  RESET = 1'b1;
  RESET_x <= 1'b0;
  #0  RESET = 1'b0;
  RESET_x <= 1'b0;
  #200633  RESET = 1'b1;
  RESET_x <= 1'b0;
  #299558  RESET = 1'b0;
  RESET_x <= 1'b0;
end

initial
begin
  s_clkE = "clkE";
  clkE = 1'b1;
  clkE_x <= 1'b0;
  #44  clkE = 1'b1;
  clkE_x <= 1'b0;
  #189985  clkE = 1'b0;
  clkE_x <= 1'b0;
  #310162  clkE = 1'b1;
  clkE_x <= 1'b0;
end

endmodule