librAry lpm;
library IEEE;
use lpm.lpm_components.all; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fsm_tb is			
end entity fsm_tb;

architecture arc_fsm_tb of fsm_tb is

--======================  fsm ports and signals ===========================================         
			signal	System_Clk_50MHz 		:  std_logic:= '0'; -- [in]
			signal	System_N_Reset			:  std_logic:= '0'; -- [in]
     	signal S_FSM_slot_number 	: integer := 90; -- signal
     	signal S_FSM_wheel_radius	: integer := 7; -- signal
--======================  motion pwm ports and signals ===========================================         
			signal	M_P_Pwm					:  std_logic:= '0'; -- [out]
			signal M_P_En      : std_logic:= '0'; -- signal
			signal S_FSM_M_P_pulse_length : integer := 0; -- signal
			



component Motion_Pwm is
	generic (
				DC: time:=17 ms;				-- changeable
				clock_period: time:=20 ns;		-- changeable 
				max_pulse: time:= 1 ms;			-- changeable
				min_pulse: time:= 2 ms;			-- changeable
				neutral_pulse: time:= 1.5 ms	-- changeable 
			);
	port	(
				Rst : In  std_logic;
				Clk : In  std_logic;
				Enable : in std_logic;
				Pwm : Out std_logic;
				pulse_length : in integer
			);
end component Motion_Pwm;



begin
  
  test : entity work.fsm
generic map (
			DC => 17 ms,
			clock_period => 20 ns,
			max_pulse => 1 ms,
			min_pulse => 2 ms,
			neutral_pulse => 1.5 ms
			)
port map	(
--======================  fsm ports ===========================================         
				System_Clk_50MHz		=> System_Clk_50MHz,	
				System_N_Reset		=> System_N_Reset,	


--======================  motion pwm ports ===========================================         
				M_P_Pwm=> M_P_Pwm
			);
		

										
motion_pwm_comp:Motion_Pwm	generic map	(	
											DC => 17 ms,
											clock_period => 20 ms,
											max_pulse => 1 ms,
											min_pulse => 2 ms,
											neutral_pulse => 1.5 ms
										)
							port map	(
											Rst => System_N_Reset,
											Clk => System_Clk_50MHz,
											Enable => M_P_En,
											Pwm => M_P_Pwm,
											pulse_length => S_FSM_M_P_pulse_length
										);

  System_Clk_50MHz <= not System_Clk_50MHz after 10 ns;
  process
    
  begin

    wait until rising_edge(System_Clk_50MHz);
    System_N_Reset <= '0';
    wait until rising_edge(System_Clk_50MHz);
    System_N_Reset <= '1';
    -- baud select
    wait until rising_edge(System_Clk_50MHz);
wait for 50 us;
 	  end process;  
end architecture arc_fsm_tb;