ARM/LPC1xxx

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General overview Cortex M0/3 Family, ©NXP.com
Comparison of the current Cortex M0/3 Family, ©NXP.com

The LPC1000-family from NXP is based on a 32-bit Cortex core from ARM and is clocked up to 150MHz. The LPC11xx-series is based on Cortex-M0, the LPC13xx (up to 72MHz), 17xx and 18xx (up to 150MHz) on Cortex-M3. Meanwhile this cores are available (even for a very low quantity) at a comparable price of current 8-bit controller as ATMega. Please find a complete list here "The ARM selection guide" (PDF) from NXP (page 2f).


General Information + User-Manuals

Key Data LPC11xx (Cortex-M0)

  • NXP's LPC11xx(L)-Serie is the lowest-priced 32-bit MCU solution in the market (3,3V) and provides several advantages
  • More than 45 DMIPS of performance is delivered at 50MHz, with extensive power optimization, at less than 10mA. (for details please see NXP-Site)
  • Feature Overview:
    • LPC1100 Serie: • I2C, SSP, UART, GPIO, • Timers and watch dog timer, • 10-bit ADC, • Flash/SRAM memory, • for further information please see 2.3 Features
    • LPC1100L series in addition to LPC1100: • Power Profile with lower power consumption in Active- und Sleep-mode, • Interne pull-ups auf VDD level, • programmable pseudo open-drain mode for GPIO pins, • WWDT with Clock Source Lock.
    • LPC11C00 Serie in addition to LPC1100: • CAN controller, • On-chip CAN driver, • On-chip CAN Transceiver (LPC11C2x), • WDT (not windowed) with Clock Source Lock .

User Manual of the LPC11-Family (PDF)

Key Data LPC12xx (Cortex-M0)

  • The Low Power LPC12xx-series (3,3V) is according to NXP (Sep2011) a Cortex-M0 with 32 to 128kB Flash, a 45 CoreMark™ Benchmark-Score at 30MHz, 2 to 8kB SRAM, and an internal 1% accurate 12MHz Oscillator.
  • Features: fMAX or 30MHz, 1 10-Bit ADC with 8 channel, 2 Comparator, 2 UARTs, 1 SSP/SPI, 1 I2C, DMA Controller, CRC Engine, 1 32-Bit, 5 Timer (16- and 32-Bit, + RTC), 13 PWM channels, up to 55 GPIOs.

User Manual of the LPC12xx-Family (PDF)

Key Data LPC13xx (Cortex-M3)

The LPC13xx-Serie (3,3V) devices are ARM Cortex-M3-based microcontrollers for embedded applications featuring a high level of integration and low power consumption and provides 8..32k Flash, 2..8k SRAM, 5 Timer (with WD), 11 PWM, 1 UART, 1IIC, 1USB, 1..2 SPI, one 8-channel /10Bit AD and a clock of up to 72MHz in a LQFP 48 housing.

User Manual of the LPC13xx-Family (PDF)

Key Data LPC17xx (Cortex-M3)

The LPC17xx-series provides moch mor periperal in a LQFP80 and a LQFP100 package. 32..512k Flash, 8..64k SRAM, 6 Timer (with WD), 6 add. PWM-units, Ethernet, mostly USB, 4 UART, 2..3IIC, 1..2 CAN, 1 SPI, 2 SSP/SPI one 6..8-channel/12bit ADC, one 10Bit DAC, Motor-Control-Units, one Encoder-Input at a clock frequenca of 100MHz(120MHz) and much more.

User Manual of the LPC17xx-Family (PDF)

Key Data LPC18xx (Cortex-M3)

TheLPC18xx-series is THE "High-Performance" Controller-Family with Cortex-M3. With a clock frequency up to 150MHz, a dual bank Flash up to 1MB, a large on-chip SRAM up to 200KB, additional peripherie eg. SPI Flash Interface (SPIFI) und State Configurable Timer (SCT), 2x High Speed USB (On-Chip HS PHY) and a MPU.

User Manual of the LPC18xx-Family (PDF)

Feature Overview: LPC18xx Flyer from NXP

Kits

From NXP a very cheap kit (app. 25€ for USB-JTAG Programmer and Debugger) is available eg. Watterott. Please see the dokumentation from NXP LPCXpresso-Entwicklungskit (PDF).


Development Environment for FREE for ALL mentioned Controller

A "free of change" environment is available here. code-red: The Eclips based environment is open up to 8k after installation and up to 128kB after a FREE registration. for Linux click here.

LPC11xx

LPC11xx - Family

Store and price information:

Block Diagram Cortex-N0, ©NXP.com

Block Diagram LPC11xx Family

LPC11xx Features

  • System:
    • ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
    • ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
    • Serial Wire Debug.
    • System tick timer.
  • Memory:
    • 32 kB (LPC1114/LPC11C14), 24 kB (LPC1113), 16 kB (LPC1112/LPC11C12), or 8 kB (LPC1111) on-chip flash programming memory.
    • 8 kB, 4 kB, or 2 kB SRAM.
    • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
  • Digital peripherals:
    • Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Number of GPIO pins is reduced for smaller packages and LPC11C22/C24.
    • GPIO pins can be used as edge and level sensitive interrupt sources.
    • High-current output driver (20 mA) on one pin.
    • High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
    • Four general purpose timers/counters with a total of four capture inputs and up to 13 match outputs.
    • Programmable WatchDog Timer (WDT).
  • Analog peripherals:
    • 10-bit ADC with input multiplexing among 8 pins.
  • Serial interfaces:
    • UART with fractional baud rate generation, internal FIFO, and RS-485 support.
    • Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only).
    • I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
    • C_CAN controller (LPC11Cxx only). On-chip CAN and CANopen drivers included.
    • On-chip, high-speed CAN transceiver (parts LPC11C22/C24 only).
  • Clock generation:
    • 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.
    • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
    • Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
    • PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.
    • Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.
  • Power control:
    • Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes.
    • Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (On LPC111x/102/202/302 only.)
    • Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
    • Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins.
    • Power-On Reset (POR).
    • Brownout detect with four separate thresholds for interrupt and forced reset.
  • Unique device serial number for identification.
  • Single 3.3 V power supply (1.8 V to 3.6 V).
  • Available as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC package.

LPC12xx

LPC12xx Family

Store and price information:

Block Diagram Cortex-N0, ©NXP.com

Block Diagram LPC12xx Family

LPC12xx Features

  • Processor core
    • ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high score of over 45 in CoreMark CPU performance benchmark testing, equivalent to 1.51/MHz.
    • ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
    • Serial Wire Debug (SWD).
    • System tick timer.
  • Memory
    • Up to 8 kB SRAM.
    • Up to 128 kB on-chip flash programming memory.
    • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
    • Includes ROM-based 32-bit integer division routines.
  • Clock generation unit
    • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
    • 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.
    • PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.
    • Clock output function with divider that can reflect the system oscillator clock, IRC clock, main clock, and Watchdog clock.
    • Real-Time Clock (RTC).
  • Digital peripherals
    • Micro DMA controller with 21 channels.
    • CRC engine.
    • Two UARTs with fractional baud rate generation and internal FIFO. One UART with RS-485 and modem support and one standard UART with IrDA.
    • SSP/SPI controller with FIFO and multi-protocol capabilities.
    • I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. I2C-bus pins have programmable glitch filter.
    • Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor, open-drain mode, programmable digital input glitch filter, and programmable input inverter.
    • Programmable output drive on all GPIO pins. Four pins support high-current output drivers.
    • All GPIO pins can be used as edge and level sensitive interrupt sources.
    • Four general purpose counter/timers with four capture inputs and four match outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).
    • Windowed WatchDog Timer (WWDT).
  • Analog peripherals
    • One 8-channel, 10-bit ADC.
    • Two highly flexible analog comparators. Comparator outputs can be programmed to trigger a timer match signal or can be used to emulate 555 timer behavior.
  • Power
    • Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
    • Processor wake-up from Deep-sleep mode via start logic using 12 port pins.
    • Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.
    • Brownout detect with three separate thresholds each for interrupt and forced reset.
    • Power-On Reset (POR).
    • Integrated PMU (Power Management Unit).
  • Unique device serial number for identification.
  • 3.3 V power supply.
  • Available as 64-pin and 48-pin LQFP package.

LPC13xx

LPC13xx Family

Selection Guide LPC13xx Family, ©NXP.com


Store and price information:

LPC1313 with 32k-Flash, 72MHz, LQFP 48 available at Darius for 3€57 (July/2011), or digikey for 2€70. Entwicklungskit INCLUDING JTAG-Programmer & Debugger at Watterott for 23€80 (July/2011)

Block Diagram LPC13xx Family, ©NXP.com


Block Diagram LPC13xx Family

LPC1313 Features

  • ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
  • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
  • 32 kB on-chip flash programming memory.
  • 8 kB SRAM.
  • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
  • UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support.
  • SSP controller with FIFO and multi-protocol capabilities.
  • Additional SSP controller on LPC1313FBD48/01.
  • I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
  • Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
  • Four general purpose counter/timers with a total of four capture inputs and 13 match outputs.
  • Programmable Watchdog Timer (WDT)
  • System tick timer.
  • Serial Wire Debug and Serial Wire Trace port.
  • High-current output driver (20 mA) on one pin.
  • High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
  • Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes.
  • Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
  • Single power supply (2.0 V to 3.6 V).
  • 10-bit ADC with input multiplexing among 8 pins.
  • GPIO pins can be used as edge and level sensitive interrupt sources.
  • Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, or the watchdog clock.
  • Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of the functional pins.
  • Brownout detect with four separate thresholds for interrupt and one thresholds for forced reset.
  • Power-On Reset (POR).
  • Integrated oscillator with an operating range of 1 MHz to 25 MHz.
  • 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature and voltage range that can optionally be used as a system clock.
  • Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator.
  • Code Read Protection (CRP) with different security levels.
  • Unique device serial number for identification.
  • Available as 48-pin LQFP package and 33-pin HVQFN package.

LPC17xx

LPC17xx Family

Selection Guide LPC13xx Family, ©NXP.com


Store and pricing information:

LPC1754 with 128K Flash, LQFP80 at Darius for 7€74 (July/2011) [LPC1751 (32k/8k) for only 5€95] and at Digikey for 6€35, the LPC1764FBD100 at TME for 7€ Develoopment Kit INCLUDING JTAG-Programmer & Debugger at Watterott for 23€80 (July/2011)

Block Diagram LPC17xx Family, ©NXP.com


Block Diagram LPC17xx Family

LPC1754 Features

  • ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
  • A Memory Protection Unit (MPU) supporting eight regions is included.
  • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
  • 128 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities.
  • 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
  • Eight channel General Purpose DMA controller
  • Serial interfaces:
  • USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation with an on-chip PHY for device and Host functions
  • Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA, Einer mit Modem I/Os und RS485 Support
  • 1 CAN controller.
  • 2 SSP controllers
  • 1 SPI controller
  • 2 I2C-bus interfaces with data rates of 1Mbit/s,
  • I2S (Inter-IC Sound)
  • 52 General Purpose I/O (GPIO) pins Any pin of ports 0 and 2 can be used to generate an interrupt.
  • 8x 12-bit Analog-to-Digital Converter (ADC) conversion rates up to 200 kHz
  • 1x 10-bit Digital-to-Analog Converter (DAC)
  • Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs.
  • One motor control PWM with support for three-phase motor control.
  • Quadrature encoder interface that can monitor one external quadrature encoder.
  • One standard PWM/timer block with external count input.
  • Real-Time Clock (RTC) with a separate power domain including 20 bytes of battery-powered backup registers, An RTC interrupt can wake up the CPU from any reduced power mode.
  • Watchdog Timer (WDT).
  • Cortex-M3 system tick timer
  • Repetitive interrupt timer
  • Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace Port options.
  • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
  • Single 3.3 V power supply (2.4 V to 3.6 V).
  • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.
  • Non-maskable Interrupt (NMI) input.
  • Wakeup Interrupt Controller (WIC)
  • Each peripheral has its own clock divider for further power savings.
  • Brownout detect with separate threshold for interrupt and forced reset.
  • On-chip Power-On Reset (POR).
  • On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
  • 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a system clock.
  • An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
  • Available as 80-pin LQFP (12 x 12 x 1.4 mm) packages.


LPC18xx

LPC18xx Family

Store and price information:

Block Diagram LPC18xx Family, ©NXP.com


Block Diagram LPC18xx Family

LPC18xx Features

DRAFT!

  • Processor core
    • ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.
    • ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
    • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
    • Non-maskable Interrupt (NMI) input.
    • JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
    • ETM and ETB support.
    • System tick timer.
  • On-chip memory (flashless parts LPC1850/30/20/10)
    • Up to 200 kB SRAM total for code and data use.
    • Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually.
    • 64 kB ROM containing boot code and on-chip software drivers.
    • 32-bit One-Time Programmable (OTP) memory for general-purpose customer use.
  • On-chip memory (parts with on-chip flash)
    • Up to 1 MB total dual bank flash memory with flash accelerator.
    • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
    • Up to 136 kB SRAM for code and data use.
    • Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually.
    • 32 kB ROM containing boot code and on-chip software drivers.
    • 32-bit One-Time Programmable (OTP) memory for general-purpose customer use.
  • Clock generation unit
    • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
    • 12 MHz internal RC oscillator trimmed to 1 % accuracy.
    • Ultra-low power RTC crystal oscillator.
    • Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
    • Clock output.
  • Serial interfaces:
    • Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per second total.
    • 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
    • One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip PHY.
    • One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.
    • USB interface electrical test software included in ROM USB stack.
    • Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support synchronous mode and a smart card interface conforming to ISO7816 specification.
    • Two C_CAN 2.0B controllers with one channel each.
    • Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
    • One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
    • One standard I2C-bus interface with monitor mode and standard I/O pins.
    • Two I2S interfaces with DMA support, each with one input and one output.
  • Digital peripherals:
    • External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
    • LCD controller with DMA support and a programmable display resolution of up to 1024H x 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
    • SD/MMC card interface.
    • Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves.
    • Up to 80 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain modes.
    • GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
    • State Configurable Timer (SCT) subsystem on AHB.
    • Four general-purpose timer/counters with capture and match capabilities.
    • One motor control PWM for three-phase motor control.
    • One Quadrature Encoder Interface (QEI).
    • Repetitive Interrupt timer (RI timer).
    • Windowed watchdog timer.
    • Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
    • Alarm timer; can be battery powered.
  • Digital peripherals available on flash-based parts LPC18xx only:
    • <tbd>
  • Analog peripherals:
    • One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
    • Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
  • Security:
    • Hardware-based AES security engine programmable through an on-chip API.
    • Two 128-bit secure OTP memories for AES key storage and customer use.
    • Unique ID for each device.
  • Power:
    • Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
    • RTC power domain can be powered separately by a 3 V battery supply.
    • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
    • Processor wake-up from Sleep mode via wake-up interrupts from various eripherals.
    • Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
    • Brownout detect with four separate thresholds for interrupt and forced reset.
    • Power-On Reset (POR).
  • Available as 100-pin, 144-pin, and 208-pin LQFP packages and as 100-pin, 180-pin, and 256-pin LBGA packages.

Development Environment

Code Red

Picture of the environment from, ©code-red-tech.com

Development Tool

Red Suite 4 NXP Edition is the low-cost upgrade for the popular LPCXpresso IDE featuring higher download limits, support for a wider range of LPC parts, and additional functionality over the free product.

Available in 256k or 512k versions (128k version FREE), Red Suite 4 NXP Edition is based on an enhanced version of the highly integrated software development environment found in the LPCXpresso IDE, and includes all the tools necessary to develop high quality software solutions in a timely and cost effective fashion.

The Red Suite IDE is based on the highly popular Eclipse platform and features many ease-of-use and Microcontroller specific enhancements. Red Suite includes the industry standard GNU tools enabling professional quality tools at low cost. The fully featured debugger supports both SWD and JTAG debugging, and features direct download to on-chip flash. Red Suite 4 NXP Edition is a significant upgrade over previous releases and includes support for Cortex-M4 based processors and new compilers and libraries which further reducing target code size. This release includes support for the new LPC1800 and LPC4300 MCUs from NXP.

Also new in this release is the Red State state machine designer and generator. (copy from Code-Red site)

Features

The Red Suite Integrated Development Environment (IDE) provides a C/C++ programming environment second to none, with syntax-coloring, source formatting, function folding, online and offline integrated help, extensive project management automation and integrated source repository support (CVS integrated or Subversion via download).

   * User extensible Wizards for creating embedded applications complete with startup code and linker scripts correctly configured for target MCU.
   * Choice of 2 diff. C libraries:
   * Comprehensive debugger provide easy way to access target resources...
   * Support for the powerful tracing facilities of the Cortex-M3 and Cortex-M4 processors, ...
   * Built-in datasheet browser
   * No assembler required with Cortex-M based devices, even for start-up code and interrupt handlers.


Peripheral and Register Views at the Debugger

The peripheral viewer provides complete visibility of all registers and bit-fields in all target peripherals in a simple tree-structured display. A powerful processor-register viewer is provided that gives access to all processors register and provides smart formatting for complex registers such as flags and status registers.

Supported Families

Device-specific support for the following families:

   * Cortex-M0 (LPC1100, LPC1200)
   * Cortex-M3 (LPC1300, LPC1700, LPC1800)
   * Cortex-M4 (LPC4300)
   * ARM7TDMI  (LPC2000)
   * ARM966    (LPC2900)
   * ARM926-EJ (LPC3100, LPC3200)


Standard Library

The download includes a "Redlib", a small footprint embedded C library, and a "Newlib", a industry standard fully featured C library.


CMSIS

a CMSIS Lib is included in the download, including a DSP-Lib

WinARM

WinARM (currently not maintained)

GNUARM

GNUARM (Linux, Windows, currently not maintained),

Yagarto

Yagarto (Windows, mit Eclipse-Integration)

CodeSourcery

CodeSourcery CodeBench Lite

Links

Search in the forum

Where to buy

Controller

Evaluation Boards

Weblinks, Foren, Communities


Development Environment