-- Lab 11-01 Implement Running Average Low Pass Filter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;

entity lab111 is
	Port ( clk : in STD_LOGIC;
		   din : in STD_LOGIC_VECTOR (15 downto 0);
		   dout : out STD_LOGIC_VECTOR (15 downto 0));
end lab111;

architecture rtl of lab111 is
	
	type tdelay is array (7 downto 0) of std_logic_vector(15 downto 0);
	
	signal sdelay : tdelay := (others => (others => '0'));
	signal res : std_logic_vector(18 downto 0) := (others => '0');

begin

	process(clk) begin
		if rising_edge(clk) then
			sdelay <= din & sdelay(7 downto 1);
		end if;
	end process;

	process(clk) begin
		if rising_edge(clk) then
			res <= signed(res) + signed(din) - signed(sdelay(0)); 
		end if;
	end process;
		
	dout <= res(18 downto 3);

end rtl;

-- cd C:/FPGA/Lab11/auto_check/